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20 v, 500 ma, low noise ldo regulator with soft start d ata sheet adp7105 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rig hts of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 analog devices, inc. all r ights reserved. technical support www.analog.com features input voltage range: 3.3 v to 20 v maximum output current: 500 ma low n oise: 15 v rms for fixed output versions psrr p erformance of 60 db at 10 khz , v out = 3.3 v reverse current protection low dropout voltage: 35 0 mv at 500 ma initial accuracy: 0.8 % accuracy over line, load, and temperature: ?2% to +1 % low quiescent curre nt : 900 a at v in = 10 v, i out = 500 ma low shutdown current: <5 0 a at v in = 12 v, s table with small 1 f ceramic output capacitor 3 fixed output voltage options: 1.8, 3.3 v and 5 v adjustable output from 1.22 v to 19 v progr ammable s oft start for inrush current control foldback current - limit and thermal overload protection user programmable precision u v lo /e nable power - good indicator 8- lead lfcsp and 8-l ead soic package s applications regulation of noise sensitive applications: adc and dac circuits, precision amplifiers, high frequency oscillators, clocks , and plls communications and infrastructure medical and healthcare industrial and instrumentation typical application circuit s figure 1. adp710 5 with fixed output voltage, 5 v figure 2. adp710 5 with adjustable output voltage, 5 v general description the adp7105 is a cmos, low dropout (ldo) linear regulator that operates from 3.3 v to 20 v and provide s up to 500 ma of output current. this high input voltage ldo is ideal for regula - tion of hi gh performance analog and mixed - signal circuits operating from 1.22 v to 1 9 v rails. using an advanced proprie - tary architecture, the adp7105 provides high power supply rejection and low nois e, and achieves excellent line and load transient response with only a small 1 f ceramic output capacitor. the adp7105 is available in three fixed output voltage options and an adjustable vers ion that allows output volt ages ranging from 1.22 v to 19 v via an external feedback divider. the adp7105 allows an external soft start capacitor to be connected to program the startup . note that throughout this data sheet, the sense function (sense) of the sense/adj pin applies to fixed output voltage model s only, whereas the adjust input function (adj) applies to adjustable output voltage model s only. for example, figure 1 shows the sense function, and figure 2 shows the adjust input function. the a dp7105 output noise voltage is 15 v rms and is i nde - pendent of the output voltage. a digital power - good output allows power system monitors to check the health of the output voltage. a user programmable precision undervoltage lockout function facilitates sequencing of multiple power supplies. the adp7105 is available in 8 - lead, 3 mm 3 mm lfcsp and 8 - lead soic packages. the lfcsp offers a very compact solution and provides excellent thermal performance for applications that require up to 50 0 ma of output current in a small, low profile footprint. v out = 5v v in = 8v pg vout vin pg ss gnd sense en/ uvlo 100k ? 100k ? 100k ? cout 1f css cin 1f on off + + 1 1641-001 v out = 5v v in = 8v pg vout vin pg gnd adj en/ uvlo 100k ? 100k ? 100k ? cout 1f cin 1f on off + + 13k ? 40.2k ? ss css 1 1641-002
adp7105 data sheet rev. 0 | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 typical application circuits ............................................................ 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 input and output capacitor, recommended specifications .. 4 absolute ma ximum ratings ............................................................ 5 thermal data ................................................................................ 5 thermal resistance ...................................................................... 5 esd caution .................................................................................. 5 pin configurations and function descriptions ........................... 6 typical performance characteristics ............................................. 7 theory of operation ...................................................................... 17 applications information .............................................................. 18 capacitor selection .................................................................... 18 programmable undervoltage lockout (uvlo) .................... 19 soft start function ..................................................................... 19 power - good feature .................................................................. 20 noise reduction of the adjustable adp7105 ........................ 20 current - limit and thermal overload protection ................. 21 thermal considerations ............................................................ 21 printed circuit board layout considerations ............................ 24 outline dimensions ....................................................................... 25 ordering guide .......................................................................... 26 revision history 7 /13 revision 0 : initial version
data sheet adp7105 rev. 0 | page 3 of 28 specifications v in = (v out + 1 v ) or 3.3 v (whichever is greater), en = v in , i out = 10 ma, c in = c o ut = 1 f, t a = 25c , unless otherwise noted. table 1 . parameter symbol test conditions /comments min typ max unit input voltage range v in 3. 3 20 v operating supply current i gnd i out = 100 a, v in = 10 v 400 a i out = 100 a, v in = 10 v, t j = ?40 c to + 125 c 900 a i out = 10 ma, v in = 10 v 450 a i out = 10 ma, v in = 10 v, t j = ?40 c to + 125 c 1050 a i out = 300 ma, v in = 10 v 750 a i out = 300 ma, v in = 10 v, t j = ?40 c to + 125 c 1400 a i out = 500 ma, v in = 10 v 90 0 a i out = 500 ma, v in = 10 v, t j = ? 40 c to + 125 c 1600 a shutdown current i gnd - sd en = gnd, v in = 12 v 40 50 a en = gnd, v in = 12 v, t j = ?40 c to + 125 c 75 a input reverse current i rev - input en = gnd, v in = 0 v, v out = 20 v 0.3 a en = gnd, v in = 0 v, v out = 20 v, t j = ?40 c to + 125 c 5 a output voltage accuracy fixed output voltage accuracy v out i out = 10 ma ? 0.8 + 0.8 % 1 ma < i out < 500 ma, v in = (v out + 1 v) to 20 v, t j = ?40 c to + 125 c ?2 +1 % adjustable outp ut voltage accuracy v adj i out = 10 ma 1.21 1.22 1.23 v 1 ma < i out < 500 ma, v in = (v out + 1 v) to 20 v, t j = ?40 c to + 125 c 1.196 1.232 v line regulation ?v out /?v in v in = (v out + 1 v) to 20 v, t j = ?40 c to + 125 c ? 0.015 + 0.015 %/v load regulatio n 1 ? v out /?i out 1 ma < i out < 500 ma 0.2 %/a 1 ma < i out < 500 ma , t j = ?40 c to + 125 c 0.75 %/a adj input bias current 2 adj i- bias 1 ma < i out < 500 ma , v in = (v out + 1 v) to 20 v, adj connected to vout 10 na sense input bias current 2 sense i- bias 1 ma < i out < 500 ma , v in = (v out + 1 v) to 20 v, sense connected to vout, v out = 1.5 v 1 a dropout voltage 3 v dropout i out = 10 ma 20 mv i out = 10 ma, t j = ?40 c to + 125 c 40 mv i out = 150 ma 10 0 mv i out = 150 ma, t j = ?40 c to + 125 c 175 mv i out = 3 00 ma 200 mv i out = 3 00 ma, t j = ?40 c to + 125 c 325 mv i out = 500 ma 350 mv i out = 500 ma, t j = ? 40 c to + 125 c 550 mv start - up time 4 t start - up c ss = 0 nf , i out = 10 ma 62 5 s c ss = 10 nf, i out = 10 ma 11.5 ms current - limit threshold 5 i limit 625 775 1000 ma pg output logic level pg output logic high pg high i oh < 1 a 1.0 v pg output logic low pg low i ol < 2 ma 0.4 v pg output threshold output vol tage falling pg fal l ? 9.2 % output voltage rising pg rise ? 6.5 % thermal shutdown thermal shutdown threshold ts sd t j rising 150 c thermal shutdown hysteresis ts sd - hys 15 c
adp7105 data sheet rev. 0 | page 4 of 28 parameter symbol test conditions /comments min typ max unit soft start source current ss i- source ss = gnd 1 a programmable en/uvlo uv lo threshold rising uvlo rise 3.3 v v in 20 v, t j = ?40 c to + 125 c 1.18 1.23 1.28 v uvlo threshold falling uvlo fal l 3.3 v v in 20 v, t j = ?40c to +125c, 10 k in series with the e nable input pin 1.13 v uvlo hysteresis current uvlo hys v en > 1.25 v, t j = ?40c to +125c 7.5 9.8 12 a enable pull -d own current i en -in en = v in 500 na start threshold v start t j = ? 40 c to + 125 c 3.2 v shutdown threshold v shutdown t j = ?40 c to + 125 c 2.45 v hysteresis 250 mv output noise out noise 10 hz t o 100 khz, v in = 5.5 v, v out = 1.8 v 15 v rms 10 hz to 100 khz, v in = 6.3 v, v out = 3.3 v 15 v rms 10 hz to 100 khz, v in = 8 v, v out = 5 v 15 v rms 10 hz to 100 khz, v in = 12 v, v out = 9 v 15 v rms 10 hz to 100 khz, v in = 5.5 v, v out = 1.5 v, adjustable mode 18 v rms 10 hz to 100 khz, v in = 12 v, v out = 5 v, adjustable mode 30 v rms 10 hz to 100 khz, v in = 20 v, v out = 15 v, adjustable mode 65 v rms power supply rejection ratio psrr 100 khz, v in = 4.3 v, v out = 3.3 v 50 db 100 khz, v in = 6 v, v out = 5 v 50 db 10 khz, v in = 4.3 v, v out = 3.3 v 60 db 10 khz, v in = 6 v, v out = 5 v 60 db 100 khz, v in = 3.3 v , v out = 1.8 v, adjustable mode 50 db 100 khz, v in = 6 v, v out = 5 v, adjustable mode 60 db 100 khz, v in = 16 v, v out = 15 v, adjustable mode 60 db 10 khz, v in = 3.3 v, v out = 1.8 v, adjustable mode 60 db 10 khz, v in = 6 v, v out = 5 v, adjustable mode 80 db 10 khz, v in = 16 v, v out = 15 v, adjustable mode 80 db 1 based on an end po int calculation using 1 ma and 5 00 ma loads. see figure 6 for typical load re gulation performance for loads less than 1 ma. 2 the adjust input function (adj) of the sense/adj pin applies to adjustable output voltage model s only; whereas the sense function (sense) applies to fixed output voltage model s only. 3 dropout voltage is defined as the input - to - output voltage diffe rential when the input voltage is set to the nominal output voltage. this specification applies only for output voltages greater than 3.0 v. 4 start - up time is defined as the time between the rising edge of en to vout being at 90 % of its nominal value. 5 c urrent - limit threshold is defined as the current at which the output voltage falls to 90% of the specified typical value. for example, the current limit for a 5 . 0 v output voltage is defined as the current that causes the output voltage to fall to 90% of 5 .0 v, or 4.5 v. input a nd output capacitor, recommended specific ations table 2 . parameter symbol test conditions /comments min typ max unit m inimum i nput and o utput c apacitance 1 c min t a = ?40 c to + 125 c 0. 7 f c apacitor esr r esr t a = ?40c to +125 c 0. 001 0.2 1 ensure that t he minimum input and output capacitance is greater than 0.7 f over the full range of operating conditions. the full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. x7r and x5r type capacitors are recommended; y5v and z5u capacitors are not recommended for use with any ldo regulator .
data sheet adp7105 rev. 0 | page 5 of 28 absolute maximum ratings table 3. parameter rating vin to gnd ?0.3 v to +22 v vout to gnd ?0.3 v to +20 v en/uvlo to gnd ?0.3 v to vin pg to gnd ?0.3 v to vin sense/adj to gnd ?0.3 v to vout ss to gnd ?0.3 v to +3.6 v storage temperature range ?65c to +150c operating junction temperature range ?40c to +125c soldering conditions jedec j-std-020 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal data absolute maximum ratings apply individually only, not in combination. the adp7105 can be damaged when the junction temperature (t j ) limit is exceeded. monitoring ambient temperature does not guarantee that t j is within the specified temperature limits. in applications with high power dissipation and poor printed circuit board (pcb) thermal resistance, the maximum ambient temperature may need to be derated. in applications with moderate power dissipation and low pcb thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. the junction temperature (t j ) of the device is dependent on the ambient temperature (t a ), the power dissipation of the device (p d ), and the junction-to-ambient thermal resistance of the package ( ja ). maximum junction temperature (t j ) is calculated from the ambient temperature (t a ) and power dissipation (p d ) using the formula t j = t a + ( p d ja ) junction-to-ambient thermal resistance ( ja ) of the package is based on modeling and calculation using a 4-layer board. the junction-to-ambient thermal resistance is highly dependent on the application and board layout. in applications where high maximum power dissipation exists, close attention to thermal board design is required. the value of ja may vary, depending on pcb material, layout, and environmental conditions. the specified values of ja are based on a 4-layer, 4 in. 3 in. circuit board. see jedec jesd51-7 and jesd51-9 for detailed information on the board construction. for additional information, see the an-772 application note , a design and manufacturing guide for the lead frame chip scale package (lfcsp) , available at www.analog.com . jb is the junction-to-board thermal characterization parameter with units of c/w. the package jb is based on modeling and calculation using a 4-layer board. jedec jesd51-12, guidelines for reporting and using electronic package thermal information , states that thermal characterization parameters are not the same as thermal resistances. jb measures the component power flowing through multiple thermal paths rather than through a single path as in thermal resistance, jb . therefore, jb thermal paths include convection from the top of the package as well as radiation from the package, factors that make jb more useful in real-world applications. maximum junction temperature (t j ) is calculated from the board temperature (t b ) and power dissipation (p d ) using the formula t j = t b + ( p d jb ) see jesd51-8 and jesd51-12 for more detailed information about jb . thermal resistance ja and jb are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. jc is a parameter for surface-mount packages with top mounted heat sinks. jc is presented here for reference only. table 4. thermal resistance package type ja jc jb unit 8-lead lfcsp 40.1 27.1 17.2 c/w 8-lead soic 48.5 58.4 31.3 c/w esd caution
adp7105 data sheet rev. 0 | page 6 of 28 pin configuration s and function descrip tions figure 3. pin configuration, lfcsp package figure 4. pin configuration, narrow - body soic package table 5 . pin function descriptions pin no. mnemonic description 1 vout regulated output voltage. bypass vout to gnd with a 1 f or greater capacitor. 2 sense/adj sense (sense). sense m easures the actual output voltage at the load and feeds it to the error amplifier. connect sense as close as possible to the load to minimize the effect of ir drop between the regulator output and the load. this function applies to fixed voltage model s only. adjust input (adj). an external resistor divider sets the output voltage. this function applies to adjustable voltage model s only. 3 gnd ground. 4 ss sof t start. a capacitor connected to this pin determines the soft start time. 5 en/uvlo enable input (en). drive en high to turn on the regulator; drive en low to turn off the regulator. for automatic startup, connect en to vin. programmable undervoltage lo ckout (uvlo). when the programmable uvlo function is used, the upper and lower thresholds are determined by the programming resistors. 6 gnd ground. 7 pg power good. this open - drain output requires an external pull - up resistor to vin or vout. if the part is in shutdown mode, current - limit mode, or thermal shutdown, or if v out falls below 90% of the nominal output voltage , pg immediately transitions low. if the power - good function is not used, the pin can be left open or connected to ground. 8 vin regulat or input supply. bypass vin to gnd with a 1 f or greater capacitor. epad exposed pad. the e xposed pad on the bottom of the package enhances thermal performance and is electrically connected to gnd inside the package. it is highly recommended that the ex posed pad be connected to the ground plane on the board. notes 1. it is highly recommended that the exposed pad on the bottom of the package be connected to the ground plane on the board. 3 gnd 4ss 1 vout 2 sense/adj 6 gnd 5 en/uvlo 8 vin 7 pg adp7105 top view (not to scale) 1 1641-003 notes 1. it is highly recommended that the exposed pad on the bottom of the package be connected to the ground plane on the board. vout 1 sense/adj 2 gnd 3 ss 4 vin 8 pg 7 gnd 6 en/uvlo 5 ad p7105 top view (not to scale) 1 1641-004
data sheet adp7105 rev. 0 | page 7 of 28 typical performance characteristics v in = 7. 5 v, v out = 5 v, i out = 10 ma , c in = c out = 1 f , t a = 25c, unless otherwise noted . figure 5. output voltage vs. junction temperature , v out = 3.3 v figure 6. output voltage vs. load current , v out = 3.3 v figure 7. output voltage vs. input voltage , v out = 3.3 v figure 8. ground current vs. junction temperature , v out = 3.3 v figure 9. ground current vs. load current , v out = 3.3 v figure 10 . ground current vs. input voltag e , v out = 3.3 v 3.25 3.27 3.29 3.31 3.33 3.35 v out (v) load = 100a load = 1ma load = 10ma load = 100ma load = 300ma load = 500ma ?40 ?5 25 85 125 t j ( c ) 1 1641-005 3.25 3.27 3.29 3.31 3.33 3.35 0.1 1 10 100 1000 v out (v) i load (ma) 1 1641-006 3.25 3.27 3.29 3.31 3.33 3.35 4 6 8 10 12 14 16 18 20 v out (v) v in (v) load = 100 a load = 1ma load = 10ma load = 100ma load = 300ma load = 500ma 1 1641-007 0 200 400 600 800 1000 1200 ground current ( a) ?40 ?5 25 85 125 t j ( c ) load = 100 a load = 1ma load = 10ma load = 100ma load = 300ma load = 500ma 1 1641-008 0 100 200 300 400 500 600 700 800 0.1 1 10 100 1000 i load (ma) ground current ( a) 1 1641-009 0 200 400 600 800 1000 1200 4 6 8 10 12 14 16 18 20 ground current ( a) v in (v) load = 100 a load = 1ma load = 10ma load = 100ma load = 300ma load = 500ma 1 1641-010
adp7105 data sheet rev. 0 | page 8 of 28 figure 11 . shutdown current vs. temperature at various input voltages figure 12 . dropout voltage vs. load current , v out = 3.3 v figure 13 . output voltage vs. input voltage (in dropout) , v out = 3.3 v figure 14 . ground current vs. input voltage (in dropout) , v out = 3.3 v figure 15 . output voltage vs. junction temperature, v out = 5 v figure 16 . output voltage vs. load current, v out = 5 v shutdown current ( a) 0 20 40 60 80 100 120 140 160 ?50 ?25 0 25 50 75 100 125 tempera ture (c) 3.3v 4.0v 6.0v 8.0v 12.0v 20.0v 1 1641-0 11 0 50 100 150 200 250 300 350 1 10 100 1000 dropout vo lt age (mv) i load (ma) v out = 3.3v t a = 25c 1 1641-012 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.1 3.2 3.3 3.4 3.5 3.6 3.7 v out (v) v in (v) load = 5ma load = 10ma load = 100ma load = 200ma load = 300ma load = 500ma 1 1641-013 0 200 400 600 800 1000 1200 1400 3.1 3.2 3.3 3.4 3.5 3.6 3.7 ground current ( a) v in (v) load = 5ma load = 10ma load = 100ma load = 200ma load = 300ma load = 500ma 1 1641-014 4.95 4.96 4.97 4.98 4.99 5.00 5.01 5.02 5.03 5.04 5.05 v out (v) load = 100a load = 1ma load = 10ma load = 100ma load = 300ma load = 500ma ?40 c ?5 c 25 c 85 c 125 c t j ( c ) 1 1641-015 4.95 4.96 4.97 4.98 4.99 5.00 5.01 5.02 5.03 5.04 5.05 0.1 1 10 100 1000 v out (v) i load (ma) 1 1641-016
data sheet adp7105 rev. 0 | page 9 of 28 figure 17 . output voltage vs. input voltage, v out = 5 v figure 18 . ground current vs. junction temperature, v out = 5 v figure 19 . ground current vs. load current, v out = 5 v figure 20 . dropout voltage vs. load current, v out = 5 v figure 21 . output voltage vs. input voltage (in dropout) , v out = 5 v figure 22 . ground current vs. input v oltage (in dropout), v out = 5 v 4.95 4.96 4.97 4.98 4.99 5.00 5.01 5.02 5.03 5.04 5.05 6 8 10 12 14 16 18 20 v out (v) v in (v) load = 100 a load = 1ma load = 10ma load = 100ma load = 300ma load = 500ma 1 1641-017 0 100 200 300 400 500 600 700 800 900 1000 25 85 125 ground current ( a) t j (c) ?40 ?5 load = 100 a load = 1ma load = 10ma load = 100ma load = 300ma 1 1641- 1 18 0 100 200 300 400 500 600 700 0.1 1 10 100 1000 ground current ( a) i load (ma) 1 1641- 1 19 0 50 100 150 200 250 300 1 10 100 1000 dropout vo lt age (mv) i load (ma) v out = 5v t a = 25c 1 1641-018 4.55 4.60 4.65 4.70 4.75 4.80 4.85 4.90 4.95 5.00 5.05 4.8 4.9 5.0 5.1 5.2 5.3 5.4 v out (v) v in (v) load = 5ma load = 10ma load = 100ma load = 200ma load = 300ma load = 500ma 1 1641-019 ?500 0 500 1000 1500 2000 2500 4.80 4.90 5.00 5.10 5.20 5.30 5.40 ground current ( a) v in (v) load = 5ma load = 10ma load = 100ma load = 200ma load = 300ma load = 500ma 1 1641-020
adp7105 data sheet rev. 0 | page 10 of 28 figure 23 . output voltage vs. junction temperature, v out = 1.8 v figure 24 . output voltage vs. load current, v out = 1.8 v figure 25 . outp ut voltage vs. input voltage, v out = 1.8 v figure 26 . ground current vs. junction temperature, v out = 1.8 v figure 27 . ground current vs. load current, v out = 1.8 v figure 28 . ground current vs. input voltage, v out = 1.8 v 1.75 1.77 1.79 1.81 1.83 1.85 v out (v) load = 100 a load = 1ma load = 10ma load = 100ma load = 300ma load = 500ma ?40 ?5 25 85 125 t j ( c ) 1 1641-021 v out (v) 1.75 1.77 1.79 1.81 1.83 1.85 0.1 1 10 100 1000 i load (ma) 1 1641-022 1.75 1.77 1.79 1.81 1.83 1.85 2 4 6 8 10 12 14 16 18 20 v out (v) v in (v) load = 100 a load = 1ma load = 10ma load = 100ma load = 300ma load = 500ma 1 1641-023 0 100 200 300 400 500 600 700 800 900 25 85 125 ground current ( a) t j (c) ?40 ?5 load = 100 a load = 1ma load = 10ma load = 100ma load = 300ma 1 1641-126 0 100 200 300 400 500 600 700 0.1 1 10 100 1000 ground current ( a) i load (ma) 1 1641-127 0 200 400 600 800 1000 1200 2 4 6 8 10 12 14 16 18 20 ground current ( a) v in (v) load = 100 a load = 1ma load = 10ma load = 100ma load = 300ma load = 500ma 1 1641-024
data sheet adp7105 rev. 0 | page 11 of 28 figure 29 . output voltage vs. junction temperature, v out = 5 v, adjustable figure 30 . output voltage vs. load current, v out = 5 v, adjustable figure 31 . output voltage vs. input voltage, v out = 5 v, adjustable figure 32 . reverse input current vs. temperature , v in = 0 v, different voltages on v out figure 33 . start- up time , v en and v in = 6 v, c in and c out = 1 f, c ss = 10 nf, i out = 10 ma, v out = 5 v figure 34 . power supply rejection ratio vs. frequency, v out = 1.8 v, v in = 3.3 v 4.98 4.99 5.00 5.01 5.02 5.03 5.04 5.05 5.06 5.07 5.08 v out (v) load = 100a load = 1ma load = 10ma load = 100ma load = 300ma load = 500ma ?40 ?5 25 85 125 t j ( c ) 1 1641-025 4.98 4.99 5.00 5.01 5.02 5.03 5.04 5.05 5.06 5.07 5.08 0.1 1 10 100 1000 v out (v) i load (ma) 1 1641-026 4.98 4.99 5.00 5.01 5.02 5.03 5.04 5.05 5.06 5.07 5.08 6 8 10 12 14 16 18 20 v out (v) v in (v) load = 100a load = 1ma load = 10ma load = 100ma load = 300ma load = 500ma 1 1641-027 0 0.5 1.0 1.5 2.0 ?40 ?20 0 20 40 60 80 100 120 140 reverse input current ( a) tempera ture (c) 3.3v 4v 5v 6v 8v 10v 12v 15v 18v 20v 1 1641-054 ch1 2.00v ch2 2.00v m2.00ms a ch1 3.00v t 5.95ms ch3 20m a 3 2 1 en v out i in 1 1641-133 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 100 1k 10k 100k 1m 10m psrr (db) frequenc y (hz) load = 500ma load = 300ma load = 100ma load = 10ma load = 1ma 1 1641-028
adp7105 data sheet rev. 0 | page 12 of 28 figure 35 . power supply reje ction ratio vs. frequency, v out = 3.3 v, v in = 4.8 v figure 36 . power supply rejection ratio vs. frequency, v out = 3.3 v, v in = 4.3 v figure 37 . power supply rejection ratio vs. frequency, v ou t = 3. 3 v, v in = 3.8 v figure 38 . power supply rejection ratio vs. frequency, v out = 5 v, v in = 6.5 v figure 39 . power supply rejection ratio vs. frequency, v out = 5 v, v in = 6 v figure 40 . power supply rejection ratio vs. frequency, v out = 5 v, v in = 5.5 v ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 100 1k 10k 100k 1m 10m psrr (db) frequenc y (hz) load = 500ma load = 300ma load = 100ma load = 10ma load = 1ma 1 1641-029 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 100 1k 10k 100k 1m 10m psrr (db) frequenc y (hz) load = 500ma load = 300ma load = 100ma load = 10ma load = 1ma 1 1641-030 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 100 1k 10k 100k 1m 10m psrr (db) frequenc y (hz) load = 500ma load = 300ma load = 100ma load = 10ma load = 1ma 1 1641-031 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 psrr (db) frequenc y (hz) 10 100 1k 10k 100k 1m 10m load = 500ma load = 300ma load = 100ma load = 10ma load = 1ma 1 1641-032 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 psrr (db) frequenc y (hz) 10 100 1k 10k 100k 1m 10m load = 500ma load = 300ma load = 100ma load = 10ma load = 1ma 1 1641-033 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 psrr (db) 10 100 1k 10k 100k 1m 10m frequenc y (hz) load = 500ma load = 300ma load = 100ma load = 10ma load = 1ma 1 1641-034
data sheet adp7105 rev. 0 | page 13 of 28 figure 41 . power supply rejection ratio vs. frequency, v out = 5 v, v in = 5.3 v figure 42 . power supply rejection ratio vs. frequency, v out = 5 v, v in = 5.2 v figure 43 . power supply rejection ratio vs. frequency, v out = 5 v, v in = 6 v, adjustable figure 44 . power supply rejection ratio vs . frequency , v out = 5 v, v in = 6 v, adjustable w ith noise reduction circuit figure 45 . power supply rejection ratio vs. headroom voltage, 100 hz, v out = 5 v figure 46 . power supply rejection ratio vs. headroom voltage, 1 khz , v out = 5 v ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 psrr (db) 10 100 1k 10k 100k 1m 10m frequenc y (hz) load = 500ma load = 300ma load = 100ma load = 10ma load = 1ma 1 1641-035 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 psrr (db) 10 100 1k 10k 100k 1m 10m frequenc y (hz) load = 500ma load = 300ma load = 100ma load = 10ma load = 1ma 1 1641-036 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 psrr (db) 10 100 1k 10k 100k 1m 10m frequenc y (hz) load = 500ma load = 300ma load = 100ma load = 10ma load = 1ma 1 1641-037 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 psrr (db) 10 100 1k 10k 100k 1m 10m frequenc y (hz) load = 500ma load = 300ma load = 100ma load = 10ma load = 1ma 1 1641-038 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 0.25 0.50 0.75 1.00 1.25 1.50 psrr (db) headroom vo lt age (v) load = 500ma load = 300ma load = 100ma load = 10ma load = 1ma 1 1641-039 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 0.25 0.50 0.75 1.00 1.25 1.50 psrr (db) headroom vo lt age (v) load = 500ma load = 300ma load = 100ma load = 10ma load = 1ma 1 1641-040
adp7105 data sheet rev. 0 | page 14 of 28 figure 47 . power supply rejection ratio vs. headroom voltage, 10 khz , v out = 5 v figure 48 . power supply rejection ratio vs. headroom voltage, 100 khz , v out = 5 v figure 49 . output noise vs. load current and output voltage, c out = 1 f figure 50 . output noise spectral density, i load = 10 ma, c out = 1 f figure 51 . load transient response, c in = c out = 1 f, i load = 1 ma to 500 ma , v out = 1.8 v, v in = 5 v figure 52 . load transient response, c in = c out = 1 f, i load = 1 ma to 500 ma , v out = 3.3 v, v in = 5 v ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 0.25 0.50 0.75 1.00 1.25 1.50 psrr (db) headroom vo lt age (v) load = 500ma load = 300ma load = 100ma load = 10ma load = 1ma 1 1641-041 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 0.25 0.50 0.75 1.00 1.25 1.50 psrr (db) headroom vo lt age (v) load = 500ma load = 300ma load = 100ma load = 10ma load = 1ma 1 1641-042 5 0 10 15 20 25 30 0.01 0.001 0.0001 0.00001 0.1 1 noise ( v rms) i load (a) 3.3v 1.8v 5v 5v adj 5v adj nr 1 1641-043 frequenc y (hz) 0.01 0.1 1 10 10 100 1k 10k 100k noise ( v/ hz) 3.3v 5v 5v adj 5v adj nr 1 1641-044 ch2 50mv ch1 500ma m 20 s a ch1 270m a 1 2 t 10% ? load current output voltage 1 1641-045 b w b w ch2 50mv ch1 500m a m 20 s a ch1 280m a 1 2 t 10.2% ? load current output voltage 1 1641-046 b w b w
data sheet adp7105 rev. 0 | page 15 of 28 figure 53 . load transient response, c in = c out = 1 f, i load = 1 ma to 500 ma , v out = 5 v, v in = 7 v figure 54 . line transient response, c in = c out = 1 f, i load = 5 00 ma, v out = 1.8 v figure 55 . line transient response, c in = c out = 1 f, i load = 500 ma, v out = 3.3 v figure 56 . line transient response, c in = c out = 1 f, i load = 5 00 ma, v out = 5 v figure 57 . line transient response, c in = c out = 1 f, i load = 1 ma, v out = 1.8 v figure 58 . line transient response, c in = c out = 1 f, i load = 1 ma, v out = 3.3 v ch2 50mv ch1 500m a m 20 s a ch1 300m a 1 2 t 10.2% ? load current output voltage 1 1641-047 b w b w ch2 10mv ch1 1v m 4 s a ch4 1.56v 1 2 t 9.8% input voltage output voltage 1 1641-048 b w b w ch2 10mv ch1 1v m 4 s a ch4 1.56v 1 2 t 9.8% input voltage output voltage 1 1641-049 b w b w ch2 10mv ch1 1v m 4 s a ch4 1.56v 1 2 t 9.8% input voltage output voltage 1 1641-050 b w b w 1 2 input voltage output voltage 1 1641-051 ch2 10mv ch1 1v m 4 s a ch4 1.56v t 9.8% b w b w 1 2 input voltage output voltage 1 1641-052 ch2 10mv ch1 1v m 4 s a ch4 1.56v t 9.8% b w b w
adp7105 data sheet rev. 0 | page 16 of 28 figure 59 . line transient response, c in = c out = 1 f, i load = 1 ma, v out = 5 v ch2 10mv ch1 1v m 4 s a ch4 1.56v 1 2 t 9.8% input voltage output voltage 1 1641-053 b w b w
data sheet adp7105 rev. 0 | page 17 of 28 theory of operation the adp7 105 is a low quiescent current, ldo linear regulat or that operates from 3.3 v to 20 v and provide s up to 500 ma of output current. the adp7105 d raw s a low 900 a of quiescent current (typical) at full load , making it ideal for battery - operated portable equipment. typical shutdown current consumption is 40 a at room temperature. optimized for use with small 1 f ceramic capacitors, the adp7105 provides excellent transient performance. figure 60 . fixed output voltage internal block diagram figure 61 . adjustable output voltage internal block diagram internally, the adp7105 consists of a reference, an error amplifier, a feedback vol tage divider, and a pmos pass transistor. output current is delivered via the pmos pass device, which is controlled by the error amplifier. the error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the diffe rence. if the feedback voltage is lower than the reference voltage, the gate of the pmos device is pulled lower, allowing more current to pass and increasing the output voltage. if the feedback voltage is higher than the reference voltage, the gate of th e pmos device is pulled higher, allowing less current to pass and decreasing the output voltage. the adp7105 is available in three fixed output voltage options, 1 . 8 v, 3.3 v, and 5 v, and in a n adjustable version with an output voltage that can be set from 1.22 v to 19 v by an external voltage divider. the output voltage can be set according to the following equation: v out = 1.22 v(1 + r1 / r2 ) figure 62 . typical adjustable output voltage application schematic ensure that t he value of r2 is less than 200 k to minimize errors in the output voltage caused by the adj input current. for example, when r1 and r2 each equal 200 k , the output voltage is 2.4 6 v. the output voltage error introduced by the adj input current is 2 mv or 0.08%, assuming a typical adj input current of 10 na at 25 c. the adp7105 uses the en/uvlo pin to enable and disable the vout pin under normal operating conditions. when en/uvlo is high, vout turns on ; when en /uvlo is low, vout turns off. for automatic startup, en/uvlo can be tied to vin. the adp7105 incorporates reverse current protection circuitry that prevents current flow backward s through the pass element when the output voltage is greater than the input voltage. a comparator senses the difference between the input and output voltages. when the difference between the input voltage and output voltage exceeds 55 mv, the body of the pfet is switc hed to v out and turned off or opened. in other words, the gate is connected to vout . shutdown vin gnd en/ uvlo vout r1 r2 1.22v reference vreg pgood pg sense ss short-circuit, thermal protect 9.8a 1 1641-055 shutdown vin gnd en/ uvlo vout r2 1.22v reference vreg pgood pg adj short-circuit, thermal protect 9.8a ss 1 1641-056 v out = 5v v in = 8v pg vout vin pg gnd adj en/ uvlo rpg 100k? r4 100k ? r3 100k ? cout 1f cin 1f on off r2 13k? + + r1 40.2k? ss css 1 1641-075
adp7105 data sheet rev. 0 | page 18 of 28 applications informa tion capacitor selection output capacitor the adp7105 is designed for operation with small, space - saving ceramic capacitors but functions with most commonly used capacitors as long as care is taken with regard to the effective series resistance (esr) value. the esr of the output capacitor affects the stability of the ldo control loop. a m inimum of 1 f capacitance with an esr of 1 ? or less is recommended to ensure the stability of the adp7105 . transient response to changes in load current is also affected by output capacitance. using a larg er value of output capacitance improves the transient response of the adp7105 to large changes in load current. figure 63 shows the transient responses for an output capacitance value of 1 f. figure 63 . output transient response, v out = 1.8 v, c out = 1 f input bypass capacitor connecting a 1 f capacitor from vin to gnd reduces the circuit sensitivity to pcb layout, especiall y when long input traces or high source impedance is encountered. if greater than 1 f of output capacitance is required, increase the input capacitor to match it. input and output capacitor properties any good quality ceramic capacitors can be used with t he adp7105 , as long as they meet the minimum capacitance and maximum esr requirements. ceramic capacitors are manufac - tured with a variety of dielectrics, each with different behavior over temperature and applied voltage. capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. x5r or x7r dielectrics with a voltage rating of 6.3 v to 25 v are recommended. y5v and z5 u dielectrics are not recommended, due to their poor temperature and dc bias characteristics. figure 64 shows the capacitance vs. voltage bias characteristic of an 0402, 1 f , 10 v, x5r capacitor. the voltage s tability of a capacitor is strongly influenced by the capacitor size and voltage rating. in general, a capacitor in a larger package or higher voltage rating exhibits better stability. the temperature varia tion of the x5r dielectric is ~ 15% over the ?40c to + 85 c temperature range and is not a function of package or voltage rating. figure 64 . capacitance vs. voltage bias characteristic use equation 1 to determine the worst - case capacitance , accounting for capacitor variation ove r temperature, component tolerance, and voltage. c eff = c bias (1 ? tempco ) (1 ? tol ) (1) where: c bias is the effective capacitance at the operating voltage. tempco is the worst - case capacitor temperature coefficient. tol is the worst - case component tolerance. in this example, the worst - case temperature coefficie nt (tempco) over ?40c to +85c is assumed to be 15% for an x5r dielectric . the tolerance of the capacitor (tol) is assumed to be 10%, and c bias is 0.94 f at 1.8 v, as shown in figure 64 . substituting these values in equation 1 yields c eff = 0.94 f (1 ? 0.15) (1 ? 0.1) = 0.719 f therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the ldo regulator overtemperature and tolerance at the chosen output voltage. to guarantee the performance of the adp7105 , it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. ch2 50mv ch1 500ma m 20 s a ch1 270m a 1 2 t 10% ? load current output voltage 1 1641-057 1.2 1.0 0.8 0.6 0.4 0.2 0 0 2 4 6 8 10 ca p aci t ance (f) volt age (v) 1 1641-058
data sheet adp7105 rev. 0 | page 19 of 28 progra m mable unde rvoltage l ockout (uvlo) the adp7105 uses the en/uvlo pin to enable and disable the vout pin under normal operating conditions. as shown in figure 65 , w hen a rising voltage on en/uvlo crosses the upper threshold, vout turns on. when a falling voltage on en/uvlo crosses the lower threshold, vout turns off. the hysteresis of the en/uvlo threshold is determined by the thevenin equivalent resistance in series with the en/uvlo pin. figure 65 . typical vout response to en /uvlo pin operation the upper and lower thresholds are user programmable and can be set using two resistors. when the en/uvlo pin voltage is below 1.2 3 v, the ldo is di sabled. when the en/uvlo pin voltage transitions above 1.2 3 v, the ldo is enabled and 10 a hysteresis current is sourced out of the pin , raising the voltage and thus providing threshold hysteresis. typically, two external resistors program the minimum ope rational voltage for the ldo. the resistance values, r1 and r2 , can be determined from the following : r1 = v hys /10 a r2 = 1.2 3 v r1 /( v in ? 1.2 3 v) where: v hys is the desired en/uvlo hysteresis level. v in is the desired turn - on voltage. hysteresis can also be achieved by connecting a resistor in series with the en/uvlo pin . for the example shown in figure 66, the e nable threshold is 2.46 v with a hysteresis of 1 v. figure 66 . typical en /uvlo pin voltage divider figure 65 shows the typical hysteresis of t he en/uvlo pin. this prevents on/off oscillations that can occur due to noise on the en /uvlo pin as it passes through the threshold points. soft start f unction for applications that require a controlled startup, the adp7105 provides a programmable soft start function. programmable soft start is useful for reducing inrush current upon startup and for providing voltage sequencing. to implement soft start, connect a small ceramic capacitor from s s to gnd. upon startup, a 1 a current source charges this capacitor. the adp7105 start - up output voltage is limited by the voltage at ss, providing a smooth ramp - up to the nominal output volt age. the soft start time is calculated b y t ss = v ref ( c ss / i ss ) where: t ss is the soft start delay . v ref is the 1.22 v reference voltage. c ss is the soft start capacitance between ss and gnd. i ss is the current sourced from ss (1 a). when the adp7105 is disabled ( by driving en low ), the soft start capacitor is discharged to gnd through an internal 5 k ? resistor. figure 67 . typical start - up behavior 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 1.25 1.50 1.75 2.00 en/uvlo (v) 2.25 2.50 2.75 3.00 1.00 0 v out , en/uvlo rise v out , en/uvlo f al l 1 1641-060 v out (v) v out = 5v v in = 8v pg vout vin pg gnd sense en/ uvlo 100k ? r2 100k ? r1 100k ? c out 1f c in 1f on off + + ss c ss 1 1641-059 time (ms) 0 1 2 3 4 5 6 7 0 5 10 15 output vo lt age (v) 2.7nf 0nf 6.8nf 10nf en 1 1641-061
adp7105 data sheet rev. 0 | page 20 of 28 power - good feature the adp7105 provides a power - good pin ( pg ) to indicate the status of the output. this open - drai n output requires an external pull - up resistor to vin or vout . if the part is in shutdown mode, current - limit mode, or thermal shutdown, or if v out falls below 90% of the nominal output voltage, the power - good pin (pg) immediately transitions low. during s oft start, the rising threshold of the power - good signal is 93.5% of the nominal output voltage. the open - drain output is held low when the adp7105 has suffi - cient input voltage to turn on the internal pg transistor. the pg transistor is terminated via a pull - up resistor to vout or vin. power - good accuracy is 93.5% of the nominal regulator output voltage when this voltage is rising, with a 90 .8 % trip point when this voltage is falling. regulato r input voltage brownouts or glitches trigger power no good signals if v out falls below 90 .8% of the nominal output voltage . a normal power - down causes the power - good signal to go low when v out falls below 90 .8 %. fi gure 68 and figure 69 show the typical power - good rising and falling threshold s over temperature. figure 68 . typical power -good threshold vs . output voltage and temperature, v out rising figure 69 . typical power -good threshold vs . output voltage and temperature, v out falling n oise r eduction of the a djustable adp7105 the ultralow output noise of the fi xed output adp7105 is achieved by keeping the ldo error amplifier in unity gain and setting the reference voltage equal to the output voltage. this architecture does not apply to the adjustabl e output voltage ldo regulator. the adjustable output adp7105 uses the more conventional architecture where the reference voltage is fixed and the error amplifier gain is a function of the outp ut voltage. the disadvantage of the conventional ldo architecture is that the output voltage noise is proportional to the output voltage. the adjustable ldo circuit can be modified slightly to reduce the output voltage noise to levels close to that of the fixed output adp7105 . the circuit shown in figure 70 adds two additional components to the output voltage setting resistor divider. c nr and r nr are add ed in parallel with r fb 1 to reduce the ac gain of the error amplifier. r nr is chosen to be equal to r fb 2 . this limits the ac gain of the error amplifier to approximately 6 db. the actual gain is the parallel combination of r nr and r fb 1 divided by r fb 2 . thi s ensures that the error amplifier always operates at greater than unity gain. c nr is chosen by setting the reactance of c nr equal to r fb 1 ? r nr at a frequency between 50 hz and 100 hz. this capacitor value sets the fre quency so that the ac gain of the error amplifier is 3 db less than its dc gain. figure 70 . noise reduction modification to adjustable ldo regulator the noise of the adjustable ldo regulator can be found by using the following formula , assuming the noise of a fixed output ldo is approximately 15 v: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + + k 13/ k 2.40/1k 1/13 1 1 v 15 based on the component values shown in figure 70 , the adp7105 has the following characteristics: ? dc gain of 4.09 ( 12.2 db) ? 3 db roll - off frequency of 59 hz ? high frequency ac gain of 1.76 ( 4.89 db) ? noise reduction factor of 1.33 (2. 59 db) ? rms noise of the adp7105 adjustable ldo without noise reduction of 27.8 v rms ? rms noise of the adp7105 adjustable ldo with noise reduc tion (assuming 15 v rms for fixed voltage option) of 19.95 v rms 0 1 2 3 4 5 6 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.0 pg (v) v out (v) 4 0 c 5 c +2 5 c +8 5 c +12 5 c 1 1641-062 0 1 2 3 4 5 6 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.0 pg (v) v out (v) ?4 0 c ?5 c +2 5 c +8 5 c +12 5 c 1 1641-063 v out = 5v v in = 8v pg vout vin pg gnd adj en/ uvlo rpg n? r4 100k ? r3 100k ? cout 1f cin 1f on off r nr 13k ? r fb2 13k ? + + r fb1 40.2k ? c nr 100nf + ss css 1 1641-064
data sheet adp7105 rev. 0 | page 21 of 28 current - limit and thermal ov erload protection the adp7105 is protected against damage due to excessive power diss ipation by current and thermal overload protection circuits. the adp7105 is designed to limit the current when the output load reaches 775 ma (typical). when the output load exceeds 775 ma, the output voltage is reduced to maintain a constant current limit. as the output voltage drops, the current is folded back to approximately 50 ma to minimize heat generation inside the ldo regulator . thermal overload protection is included, which limits the junction temperature to a maximum of 150c (typical). under extreme conditions (that is, high ambient temperature and/or high power dissipation) when the junction temperature starts to rise above 150c, the output is turned off, reducing the output current to zero. when the junction temperature falls below 135 c, the output is turned on again, and output current is restored to its operating value. consider the case where a hard short from vout to ground occurs. at first, the adp7105 limits the current so that only 775 ma is co nducted into the short. if self heating of the junction is great enough to cause its temperature to rise above 150c, thermal s hutdown is activate d , turning off the output a nd reducing the output current to zero. as the junction temperature cools and falls below 135c, the output turns on and conducts 775 ma into the short, again causing the junction temperature to rise above 150c. this thermal oscillation between 135c and 150c causes a current oscillation between 775 ma and 0 ma that continues as long as the short remains at the outpu t. current - limit and thermal limit protections are intended to protect the device against accidental overload conditions. for reliable operation, device power dissipation must be externally limited so that the junction temperature does not exceed 125 c. thermal consideratio ns in applications with a low input - to - output voltage differential, the adp7105 does not dissipate much heat. however, in applications with high ambient temperature and/or high input voltage, the heat dissipated in the package may become significant enough that it cause s the junction temperature of the die to excee d the maximum junction temperature of 125 c. when the junction temperature exceeds 150c, the regulator enters thermal shutdown. it recovers only after the junction temper ature decrease s below 135c to prevent any permanent damage. therefore, thermal anal ysis for the chosen application is very important to guarantee reliable performance over all conditions. the junction temperature of the die is the sum of the ambient temperature of the environment and the tempera - ture rise of the package due to the power dissipation, as shown in equation 2. to guarantee reliable operation, the junction temperature of the adp7105 must not exceed 125c. to ensure that the junction temperature stays below this max imum value, the user must be aware of the parameters that contribute to junction temperature changes. these parameters include ambient temperature , power dissipation in the power device, and thermal resistances between the junction and ambient air ( ja ). the ja value is dependent on the package assembly compounds that are used and the amount of copper used to solder the package gnd pins to the pcb. table 6 shows typical ja v alues for the 8 - lead soic and 8 -l ead lfcsp package s for various pcb copper sizes. table 7 shows the typical jb values for the 8 - lead soic and 8 - lead lfcsp with pcb area . table 6 . typical ja values copper size (mm 2 ) ja (c/w) lfcsp soic 25 1 165.1 167.8 100 125.8 111 500 68.1 65.9 1000 56.4 56.1 6400 42.1 45.8 1 device soldered to minimum size pin traces. table 7 . typical jb values with p cb area model jb (c/w) 8- lead lfcsp 1 15.1 8- lead soic 31.3 1 note that the jb value for the lfcsp package accounts for pcb area , which is being used as a heat sink via the exposed pad, whereas the value in ta ble 4 is per the jedec standard. the junction temperature of the adp7105 is calculated from the following equation: t j = t a + ( p d ja ) (2) where: t a is the ambient temperature. ja is the ju nction - to - ambient thermal resistance. p d is the power dissipation in the die, given by p d = [( v in ? v out ) i load ] + ( v in i gnd ) (3) where: v in and v out are the input and output voltages, respectively. i load is the load current. i gnd is the ground current . power dissipation due to ground current is quite small and can be ignored. therefore, the junction temperature equation simplifies to the following: t j = t a + {[( v in ? v out ) i load ] ja } (4) as shown in equation 4, for a given ambient temperature , inp ut - to - output voltage differential, and continuous load current, a minimum copper size requirement for the pcb exists to ensure that the junction temperature does not rise above 125c. figure 71 to figure 76 show junction temperature calculations for different ambient temperatures, power dissipation, and areas of pcb copper.
adp7105 data sheet rev. 0 | page 22 of 28 figure 71 . lfcsp, t a = 25c figure 72 . lfcsp , t a = 50c figure 73 . lfcsp, t a = 85c figure 74 . soic, t a = 25c figure 75 . soic, t a = 50c figure 76 . soic, t a = 85c 25 35 45 55 65 75 85 95 105 1 15 125 135 145 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 junction temper a ture (c) total power dissi pa tion (w) 6400mm 2 500mm 2 25mm 2 t j max 1 1641-065 junction temper a ture (c) 50 60 70 80 90 100 1 10 120 130 140 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 total power dissi pa tion (w) 6400mm 2 500mm 2 25mm 2 t j max 1 1641-066 junction temper a ture (c) 65 75 85 95 105 1 15 125 135 145 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 total power dissi pa tion (w) 6400mm 2 500mm 2 25mm 2 t j max 1 1641-067 25 35 45 55 65 75 85 95 105 1 15 125 135 145 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 total power dissi pa tion (w) junction temper a ture (c) 6400mm 2 500mm 2 25mm 2 t j max 1 1641-068 50 60 70 80 90 100 1 10 120 130 140 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 total power dissi pa tion (w) junction temper a ture (c) 6400mm 2 500mm 2 25mm 2 t j max 1 1641-069 65 75 85 95 105 1 15 125 135 145 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 total power dissi pa tion (w) junction temper a ture (c) 6400mm 2 500mm 2 25mm 2 t j max 1 1641-070
data sheet adp7105 rev. 0 | page 23 of 28 in the case where the board temperature is known, use the jb thermal characterization parameter to estimate the junction temperature rise (see figure 77 and figure 78 ). maximum junctio n temperature (t j ) is calculated from the board tempera - ture (t b ) and power dissipation (p d ) using the following formula: t j = t b + ( p d jb ) (5) the typical value of jb is 15.1c/w for the 8 - lead lfcsp package and 31.3c/w for the 8 - lead soic package (s ee table 7 ). figure 77 . lfcsp figure 78 . soic total power dissi pa tion (w) junction temper a ture (t j ) 0 20 40 60 80 100 120 140 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 t b = 25c t b = 50c t b = 65c t b = 85c t j max 1 1641-071 total power dissi pa tion (w) junction temper a ture (t j ) 0 20 40 60 80 100 120 140 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 t b = 25c t b = 50c t b = 65c t b = 85c t j max 1 1641-072
adp7105 data sheet rev. 0 | page 24 of 28 printed circuit b oard layout consideration s heat dissipation from the package can be improved by increasing t he amount of copper attached to the pins of the adp7105 . however, as shown in table 6 , a point of diminishing returns is eventually reached, beyond wh ich an increas e in the co pper size does not yield significant heat dissipation benefits . place t he input capacitor as close as possible to the v in and gnd pins. place t he output capacitor as close as possible to the v out and gnd pins . use of 0805 or 0603 s ize capacitors and resistors achieve s the smallest possible footprint solution on boards where space is limited . figure 79 . example lfcsp pcb layout figure 80 . example soic pcb layout 1 1641-073 1 1641-074
data sheet adp7105 rev. 0 | page 25 of 28 outline dimensi ons figure 81 . 8- lead lead frame chip scale package [lfcsp_wd] 3 mm 3 mm body, very very thin, dual lead (cp -8- 5) dimensions shown in millimeters figure 82 . 8- lead standard small outline package, wi th exposed pad [soic_n_ep] narrow body (rd -8- 2) dimensions shown in millimeters pin 1 indic at or (r 0.2) bottom view top view 1 4 8 5 index are a sea ting plane 0.80 0.75 0.70 0.30 0.25 0.18 0.05 max 0.02 nom 0.80 max 0.55 nom 0.20 ref 0.50 bsc coplanarity 0.08 2.48 2.38 2.23 1.74 1.64 1.49 0.50 0.40 0.30 compliant to jedec standards mo-229-weed-4 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 02-05-2013-b 0.20 min exposed pa d 3.10 3.00 sq 2.90 compliant t o jedec s t andards ms-012-a a 06-03-20 1 1-b 1.27 0.40 1.75 1.35 2.41 0.356 0.457 4.00 3.90 3.80 6.20 6.00 5.80 5.00 4.90 4.80 0.10 max 0.05 nom 3.81 ref 0.25 0.17 8 0 0.50 0.25 45 coplanarit y 0.10 1.04 ref 8 1 4 5 1.27 bsc sea ting plane for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. bot t om view top view 0.51 0.31 1.65 1.25 3.098
adp7105 data sheet rev. 0 | page 26 of 28 ordering guide model 1 temperature range output voltage (v) package description package option branding adp 7105 acpz - 1.8 -r7 ? 40 c to + 125 c 1.8 8- lead lfcsp_wd cp -8-5 lns adp71 05 acpz - 3.3 -r7 ? 40 c to + 125 c 3.3 8- lead lfcsp_wd cp -8-5 lnt adp 7105 acpz - 5.0 -r7 ? 40 c to + 125 c 5 8- lead lfcsp_wd cp -8-5 lnu adp 7105 acpz -r2 ? 40 c to + 125 c adjustable 8- lead lfcsp_wd cp -8-5 lnv adp 7105 acpz -r7 ? 40 c to + 125 c adjustable 8- lead lfcsp_wd cp-8-5 lnv adp 7105 ardz - 1.8 ? 40 c to + 125 c 1.8 8- lead soic_n_ep rd -8-2 adp 7105 ardz - 1.8 -r7 ? 40 c to + 125 c 1.8 8- lead soic_n_ep rd -8-2 adp 7105 ardz - 3.3 ? 40 c to + 125 c 3.3 8- lead soic_n_ep rd -8-2 adp 7105 ardz - 3.3 -r7 ? 40 c to + 125 c 3.3 8- lead soic_n_ep rd -8-2 adp 7105 ardz - 5.0 ? 40 c to + 125 c 5 8 - lead soic_n_ep rd - 8 - 2 adp 7105 ardz - 5.0 -r7 ? 40 c to + 125 c 5 8- lead soic_n_ep rd -8-2 adp 7105 ardz ? 40 c to + 125 c adjustable 8- lead soic_n_ep rd -8-2 adp 7105 ardz -r7 ? 40 c to + 125 c adjustable 8- lead soic_n_ep rd -8-2 1 z = rohs compliant part.
data sheet adp7105 rev. 0 | page 27 of 28 notes
adp7105 data sheet rev. 0 | page 28 of 28 notes ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d 11641 -0- 7/13(0)

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